Recently, the operating speed of the CPU has been improved markedly to such an extent as to exceed the operating speed of DRAMs, with the result that there arises a problem in that the operating speed of the DRAM is slower than that of the CPU.
To overcome the above-mentioned problem, various configurations have been so far considered such that the main memory section including DRAMs is composed of a plurality of banks, the memory device is operated in an interleave mode, etc. In the conventional configuration as described above, however, since the operating speed of the memory device has been apparently increased relative to that of the CPU by executing the memory access to a plurality of banks only in parallel to each other, there exist other problems in that the control method of the memory device and further the peripheral circuits of the memory device have been both complicated.
In particular, when the conventional memory device is incorporated with a relatively small-scaled computer system (e.g., minicomputer, work station, etc.), the system is complicated in particular. In more detail, when the memory bank access method or the memory interleave method is adopted for the relatively small-scaled system, the hardware configuration becomes complicated, so that the system cost and the system size both increases.
In addition, when the operating frequency of the CPU has been increased to the degree of 50 MHz or 100 MHz, it is not easy to utilize the memory device effectively. In other words, a more ingenious memory architecture is required for a high operating speed CPU, so that the memory system is further complicated.
On the other hand, the memory device of pipeline operation has been so far proposed to overcome the problem with respect to the memory system complication. When the internal circuits of the memory device are simply operated in pipeline mode, however, the operating speed of the memory device is determined on the basis of the data read speed from the core section. In other words, there exists a problem in that it has been so far difficult to increase the operating speed of the memory device up to that of the high speed CPU.